This invention relates to testing of integrated circuits and, more particularly, to accelerated voltage testing of integrated circuit devices.
Accelerated testing is used commonly when testing integrated circuit devices for determining which devices are expected to fail prematurely during normal use. Accelerating the life of an integrated circuit device is a function of a stress voltage, a temperature at which the device is stressed, and a time duration that the device is subjected to the stress condition.
Generally during testing procedures, the various circuit elements are stressed sequentially in patterns and groups. For example, in testing dynamic random access memory (DRAM) devices, it is common to assert only four of sixteen thousand wordlines at a time for stress testing. Thus a subset of the circuit elements is stressed for a period and then another subset is tested. A test engineer must accumulate on-time and off-time data relating to all of the circuit elements being tested so that the total time for circuit element stressing can be calculated. This complicates the testing procedure.
Another factor that complicates testing procedures is a need to stress transfer device gate insulators by applying a difference of potential between bitlines and wordlines. Generally the bitlines are paired as complementary signal pairs, each lead of pair is connected to a different output of a sense amplifier. For a stress condition to be placed on a single transfer device, its wordline is asserted to a high stable voltage, an xe2x80x9conxe2x80x9d state, and the associated bitline is driven to a low voltage. For a given test cycle and because of the complementary pairs of bitlines, the test procedure can stress only the circuit devices connected either to the true or the complement side of the bitlines.
Thus integrated circuit devices have required a large amount of time for stress testing procedures. Only a few wordlines are asserted and at most half of the bitlines are driven to the desired voltage level.
These and other problems are solved by either a wordline stress arrangement or a cell initialization arrangement included in an array of storage cells.
In the wordline stress arrangement, a plurality of wordlines are run across the array. Each wordline is connected with the gates of transfer transistors of a row of the storage cells. A decoder, responsive to a control signal, simultaneously applies a supply voltage to the wordlines.
The supply voltage may be provided by a selectable magnitude external source.
In the cell initialization arrangement, a plurality of complementary pairs of bitlines are run across the array. Each complementary pair of the bitlines interconnects with the storage cells in a separate column of the array. A precharge circuit is arranged for precharging the bitlines to a precharge voltage. A precharge disabling circuit, responsive to the control signal, disables the precharge circuit from applying the precharge voltage and supplies an alternative voltage to the pairs of bitlines. A separate amplifier is connected with each separate pair of complementary bitlines. A control circuit, responsive to the control signal, disables operation of the amplifiers when the alternative voltage is supplied to the pairs of bitlines.
These wordline stress and cell initialization arrangements enable very significant test time saving procedures to be undertaken for the purpose of accelerated voltage testing of integrated circuit devices.
Burn-in stress testing can be eliminated for determining integrated circuit devices that are likely to fail prematurely during normal use.